Challenging the Xeon

So what caused us to investigate the IBM POWER8 as a viable alternative to the mass market Xeon E5s and not simply the high-end quad (and higher) socket Xeon E7 parts? A lot. IBM sold its x86 server division to Lenovo. So there is only one true server processor left at IBM: the POWER family. But more importantly, the OpenPOWER fondation has a lot of momentum since its birth in 2013. IBM and the OpenPOWER Foundation Partners like Google, NVIDIA, and Mellanox are all committed to innovating around the POWER processor-based systems from the chip level up through the whole platform. The foundation has delivered some tangible results:

  • Open Firmware which includes both the firmware to boot the hardware (similar to the BIOS) ...
  • ... as OPAL (OpenPOWER Abstraction Layer) to boot and launch a hypervisor kernel.
  • OpenBMC
  • Cheaper and available to third parties (!) POWER8 chips
  • CAPI over PCIe, to make it easier to link the POWER8 to GPUs (and other PCIe cards)
  • And much more third party hardware support (Mellanox IB etc.)
  • A much large software ecosystem (see further)

The impact of opening up firmware under the Apache v2 license and BMC (IBM calls it "field processor") code should not be underestimated. The big hyperscale companies - Google, Amazon, Microsoft, Facebook, Rackspace - want as much control over their software stack as they can.

The resuls are that Google is supporting the efforts and Rackspace has even built their own OpenPOWER server called "Barreleye". While Google has been supportive and showing of proof of concepts, Rackspace is going all the way:

... and aim to put Barreleye in our datacenters for OpenStack services early next year.

The end result is that the complete POWER platform, once only available in expensive high end servers, can now be found inside affordable linux based servers, from IBM (S8xxL) and third parties like Tyan. The opinions of usual pundits range from "too little, too late" to "trouble for Intel". Should you check out a POWER8 based server before you order your next Xeon - Linux server? And why? We started with analyzing the available benchmarks carefully.

A Real Alternative? Reading the Benchmarks
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  • FunBunny2 - Friday, November 6, 2015 - link

    "The z10 processor was co-developed with and shares many design traits with the POWER6 processor, such as fabrication technology, logic design, execution unit, floating-point units, bus technology (GX bus) and pipeline design style, i.e., a high frequency, low latency, deep (14 stages in the z10), in-order pipeline." from the Wiki.

    Yes, the z continues the CISC ISA from the 360 (well, sort of) rather than hardware RISC, but as Intel (amongst others) has demonstrated, CISC ISA doesn't have to be in hardware. In fact, the 360/30 (lowest tier) was wholly emulated, as was admitted then. Today, we'd say "micro-instructions". All those billions of transistors could have been used to implement X86 in hardware, but Intel went with emulation, sorry micro-ops.

    What matters is the underlying fab tech. That's not going anywhere.
    Reply
  • FunBunny2 - Friday, November 6, 2015 - link

    ^^ should have gone to KevinG!! Reply
  • Kevin G - Saturday, November 7, 2015 - link

    The GX bus in the mainframes was indeed shared by POWER chips as that enabled system level component sharing (think chipsets).

    However, attributes like the execution unit and the pipeline depth are different between the POWER6 and z10. At a bird's eye view, they do look similar but the implementation is genuinely different.

    Other features like SMT were introduced with the POWER5 but only the most recent z13 chip has 2 way SMT. Features like out-of-order execution, SMT, SIMD were once considered too exotic to validate in the mainframe market that needed absolute certainty in its hardware states. However, recent zArch chips have implemented these features, sometimes decades after being introduced in POWER.

    The other thing is that IBM has been attempting to get get more and more of the zArch instruction set to be executed by hardware and no microcode. Roughly 75% to 80% of instructions are handled by microcode (there is a bit of a range here as some are conditional to use microcode).
    Reply
  • JohanAnandtech - Saturday, November 7, 2015 - link

    I believe that benchmark uses about 8 threads and not very well either? Secondly, it is probably very well optimized for SSE/AVX. So you can imagine that the POWER8 will not be very good at it, unless we manually optimize it for Altivec/VSX. And that is beyond my skills :-) Reply
  • UrQuan3 - Monday, December 21, 2015 - link

    I'm sure no one is still reading this as I'm posting over a month later, but...

    I tested handbrake/x264 on a bunch of cross-platform builds including Raspberry Pi 2. I found it would take 24 RPi2s to match a single i5-4670K. That was a gcc compiled handbrake on Raspbian vs the heavily optimized DL copy for Windows. Not too bad really. Also, x264 seems to scale fairly well with the number of cores. Still, POWER8 unoptimized would be interesting, though not a fair test.

    BTW, I'd encourage you to use a more standard Linux version than 6-month experimental little-endian version of Ubuntu. The slides you show advertise support for Ubuntu 14.04 LTS, not 15.04. For something this new, you may need the latest, but that is often not the case.
    Reply
  • stun - Friday, November 6, 2015 - link

    @Johan You might want to fix "the platform" hyperlink at the bottom of page 4. It is invalid. Reply
  • JohanAnandtech - Friday, November 6, 2015 - link

    Thanks and fixed. Reply
  • Ahkorishaan - Friday, November 6, 2015 - link

    Couldn't read past the graphic on page 1. It's 2015 IBM, time to use a font that doesn't look like a toddler's handwriting. Reply
  • xype - Sunday, November 8, 2015 - link

    To be fair, it seems that the slide is meant for management types… :P Reply
  • Jtaylor1986 - Friday, November 6, 2015 - link

    Using decimals instead of commas to denote thousands is jarring to your North American readers. Reply

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