Apple's Cyclone Microarchitecture Detailedby Anand Lal Shimpi on March 31, 2014 2:10 AM EST
The most challenging part of last year's iPhone 5s review was piecing together details about Apple's A7 without any internal Apple assistance. I had less than a week to turn the review around and limited access to tools (much less time to develop them on my own) to figure out what Apple had done to double CPU performance without scaling frequency. The end result was an (incorrect) assumption that Apple had simply evolved its first ARMv7 architecture (codename: Swift). Based on the limited information I had at the time I assumed Apple simply addressed some low hanging fruit (e.g. memory access latency) in building Cyclone, its first 64-bit ARMv8 core. By the time the iPad Air review rolled around, I had more knowledge of what was underneath the hood:
As far as I can tell, peak issue width of Cyclone is 6 instructions. That’s at least 2x the width of Swift and Krait, and at best more than 3x the width depending on instruction mix. Limitations on co-issuing FP and integer math have also been lifted as you can run up to four integer adds and two FP adds in parallel. You can also perform up to two loads or stores per clock.
With Swift, I had the luxury of Apple committing LLVM changes that not only gave me the code name but also confirmed the size of the machine (3-wide OoO core, 2 ALUs, 1 load/store unit). With Cyclone however, Apple held off on any public commits. Figuring out the codename and its architecture required a lot of digging.
Last week, the same reader who pointed me at the Swift details let me know that Apple revealed Cyclone microarchitectural details in LLVM commits made a few days ago (thanks again R!). Although I empirically verified many of Cyclone's features in advance of the iPad Air review last year, today we have some more concrete information on what Apple's first 64-bit ARMv8 architecture looks like.
Note that everything below is based on Apple's LLVM commits (and confirmed by my own testing where possible).
|Apple Custom CPU Core Comparison|
|Apple A6||Apple A7|
|ARM ISA||ARMv7-A (32-bit)||ARMv8-A (32/64-bit)|
|Issue Width||3 micro-ops||6 micro-ops|
|Reorder Buffer Size||45 micro-ops||192 micro-ops|
|Branch Mispredict Penalty||14 cycles||16 cycles (14 - 19)|
|Load Latency||3 cycles||4 cycles|
|Indirect Branch Units||0||1|
|L1 Cache||32KB I$ + 32KB D$||64KB I$ + 64KB D$|
As I mentioned in the iPad Air review, Cyclone is a wide machine. It can decode, issue, execute and retire up to 6 instructions/micro-ops per clock. I verified this during my iPad Air review by executing four integer adds and two FP adds in parallel. The same test on Swift actually yields fewer than 3 concurrent operations, likely because of an inability to issue to all integer and FP pipes in parallel. Similar limits exist with Krait.
I also noted an increase in overall machine size in my initial tinkering with Cyclone. Apple's LLVM commits indicate a massive 192 entry reorder buffer (coincidentally the same size as Haswell's ROB). Mispredict penalty goes up slightly compared to Swift, but Apple does present a range of values (14 - 19 cycles). This also happens to be the same range as Sandy Bridge and later Intel Core architectures (including Haswell). Given how much larger Cyclone is, a doubling of L1 cache sizes makes a lot of sense.
On the execution side Cyclone doubles the number of integer ALUs, load/store units and branch units. Cyclone also adds a unit for indirect branches and at least one more FP pipe. Cyclone can sustain three FP operations in parallel (including 3 FP/NEON adds). The third FP/NEON pipe is used for div and sqrt operations, the machine can only execute two FP/NEON muls in parallel.
I also found references to buffer sizes for each unit, which I'm assuming are the number of micro-ops that feed each unit. I don't believe Cyclone has a unified scheduler ahead of all of its execution units and instead has statically partitioned buffers in front of each port. I've put all of this information into the crude diagram below:
Unfortunately I don't have enough data on Swift to really produce a decent comparison image. With six decoders and nine ports to execution units, Cyclone is big. As I mentioned before, it's bigger than anything else that goes in a phone. Apple didn't build a Krait/Silvermont competitor, it built something much closer to Intel's big cores. At the launch of the iPhone 5s, Apple referred to the A7 as being "desktop class" - it turns out that wasn't an exaggeration.
Cyclone is a bold move by Apple, but not one that is without its challenges. I still find that there are almost no applications on iOS that really take advantage of the CPU power underneath the hood. More than anything Apple needs first party software that really demonstrates what's possible. The challenge is that at full tilt a pair of Cyclone cores can consume quite a bit of power. So for now, Cyclone's performance is really used to exploit race to sleep and get the device into a low power state as quickly as possible. The other problem I see is that although Cyclone is incredibly forward looking, it launched in devices with only 1GB of RAM. It's very likely that you'll run into memory limits before you hit CPU performance limits if you plan on keeping your device for a long time.
It wasn't until I wrote this piece that Apple's codenames started to make sense. Swift was quick, but Cyclone really does stir everything up. The earlier than expected introduction of a consumer 64-bit ARMv8 SoC caught pretty much everyone off guard (e.g. Qualcomm's shift to vanilla ARM cores for more of its product stack).
The real question is where does Apple go from here? By now we know to expect an "A8" branded Apple SoC in the iPhone 6 and iPad Air successors later this year. There's little benefit in going substantially wider than Cyclone, but there's still a ton of room to improve performance. One obvious example would be through frequency scaling. Cyclone is clocked very conservatively (1.3GHz in the 5s/iPad mini with Retina Display and 1.4GHz in the iPad Air), assuming Apple moves to a 20nm process later this year it should be possible to get some performance by increasing clock speed scaling without a power penalty. I suspect Apple has more tricks up its sleeve than that however. Swift and Cyclone were two tocks in a row by Intel's definition, a third in 3 years would be unusual but not impossible (Intel sort of committed to doing the same with Saltwell/Silvermont/Airmont in 2012 - 2014).
Looking at Cyclone makes one thing very clear: the rest of the players in the ultra mobile CPU space didn't aim high enough. I wonder what happens next round.
Post Your CommentPlease log in or sign up to comment.
View All Comments
Alexey291 - Monday, March 31, 2014 - linkTegra 3 is one of the reasons why RT didn't take off.
There are other reasons but its still one of the reasons.
techconc - Monday, March 31, 2014 - linkResting the Surface RT's failure on the Tegra 3 is a bit of a stretch. Having slow storage, low screen resolution, abysmal ecosystem / product catalog, etc. might have had something to do with it. Geeks in forums like this will obsess over CPU/GPU, etc. but "the masses" do not.
Wilco1 - Friday, April 4, 2014 - linkRT used the slowest T3 rather than the fastest - not a fault of Tegra 3.
Kidster3001 - Monday, April 7, 2014 - linkCrippled Windows and on a tablet to boot. Two big reasons.
techconc - Monday, March 31, 2014 - linkThe Tegra lines weren't terrible, but they didn't live up to their hype either. With nVidia's GPU pedigree, people expected the Tegra line of chips to be best in class, at least in that regard. Considering they are using ARM reference designs for the CPU, this was their place to distinguish their products. The first 3 Tegra generations were "flops" at least in that regard. Tegra 4 is respectable. K1 looks like they finally understand this equation. Still, when you pre-announce products so far in advance, you get setup for a let down. Future tech from any company always looks good. How will the K1 Denver Soc compare to say Apple's A8? That's the chip it will be competing against, not the A7.
StevenN - Monday, March 31, 2014 - linkTegra 2 was a dog and there is little other way to look at it. Think Xoom. The Tegra 2 lacked the Neon with Nvidia hoping developers would hand code to their GPU. It hurt the overall performance for graphics and computationally intensive apps.
UpSpin - Monday, March 31, 2014 - linkIf you look closer, the Tegra SoCs were and are one of the fastest and most efficient available for such a small die size. NV were the first to go quad core with a companion core. And the Tegra K1 is the first SoC to fully support OpenGL. So why doesn't it get used that much if it's so good?
Because it lacks a modem! Requiring an external modem increases PCB size, part costs and most importantly: Power consumption. That's the one and only reason everyone goes with Qualcomm. Or why do you think do some Galaxy smartphones get sold in two versions with either a Samsung or a Qualcomm SoC?
And would Win RT have been a success, so would have NV benefited from it, too.
NV tries to adress the modem issue (see Tegra 4i) but it seems to be not so simple and takes a lot of time, and probably money, too.
Maybe that's the reason NV is (at least it seems so to me) abandoning the smartphone market (just as TI did) and focusing on game consoles (Shield, Ouya), embedded market (Jetson TK1, Powering the Tesla infotainment system, and future Audi, GM, Honda, ... cars) and high performance computing. In all these areas NVidia is much more successful than Qualcomm.
grahaman27 - Monday, March 31, 2014 - linkMy biggest qualm with the tegra 4i (and nvidia's i500a modem) is the lack of CDMA support. because of this, they are choosing not to compete in the US.
But, hopefully in the future CMDA becomes non-essential as LTE dominates. It looks like that future is only a year or two out for verizon (and who cares about sprint, really.)
Kidster3001 - Monday, April 7, 2014 - linkCompanion core or big.LITTLE. either way it's a hack. You're far better off designing a core that can scale up and down the voltage/performance scale.
Anders CT - Tuesday, April 1, 2014 - linkTegra 4 was not a flop on technical grounds. It is a very capable performer in tablets, with decent power consumption, when reasonably clocked. The Tegra 4 can certainly compete with Apples A7 in performance, and that is with a smaller die area.
It hasn't had too many design wins, mainly because it was a couple of months delayed, because the i500 modem was a year delayed, and because of bad experiences with the dissapointing Tegra 3 and NVIDIA hypefest in general.