OoOE

You’re going to come across the phrase out-of-order execution (OoOE) a lot here, so let’s go through a quick refresher on what that is and why it matters.

At a high level, the role of a CPU is to read instructions from whatever program it’s running, determine what they’re telling the machine to do, execute them and write the result back out to memory.

The program counter within a CPU points to the address in memory of the next instruction to be executed. The CPU’s fetch logic grabs instructions in order. Those instructions are decoded into an internally understood format (a single architectural instruction sometimes decodes into multiple smaller instructions). Once decoded, all necessary operands are fetched from memory (if they’re not already in local registers) and the combination of instruction + operands are issued for execution. The results are committed to memory (registers/cache/DRAM) and it’s on to the next one.

In-order architectures complete this pipeline in order, from start to finish. The obvious problem is that many steps within the pipeline are dependent on having the right operands immediately available. For a number of reasons, this isn’t always possible. Operands could depend on other earlier instructions that may not have finished executing, or they might be located in main memory - hundreds of cycles away from the CPU. In these cases, a bubble is inserted into the processor’s pipeline and the machine’s overall efficiency drops as no work is being done until those operands are available.

Out-of-order architectures attempt to fix this problem by allowing independent instructions to execute ahead of others that are stalled waiting for data. In both cases instructions are fetched and retired in-order, but in an OoO architecture instructions can be executed out-of-order to improve overall utilization of execution resources.

The move to an OoO paradigm generally comes with penalties to die area and power consumption, which is one reason the earliest mobile CPU architectures were in-order designs. The ARM11, ARM’s Cortex A8, Intel’s original Atom (Bonnell) and Qualcomm’s Scorpion core were all in-order. As performance demands continued to go up and with new, smaller/lower power transistors, all of the players here started introducing OoO variants of their architectures. Although often referred to as out of order designs, ARM’s Cortex A9 and Qualcomm’s Krait 200/300 are mildly OoO compared to Cortex A15. Intel’s Silvermont joins the ranks of the Cortex A15 as a fully out of order design by modern day standards. The move to OoO alone should be good for around a 30% increase in single threaded performance vs. Bonnell.

Pipeline

Silvermont changes the Atom pipeline slightly. Bonnell featured a 16 stage in-order pipeline. One side effect to the design was that all operations, including those that didn’t have cache accesses (e.g. operations whose operands were in registers), had to go through three data cache access stages even though nothing happened during those stages. In going out-of-order, Silvermont allows instructions to bypass those stages if they don’t need data from memory, effectively shortening the mispredict penalty from 13 stages down to 10. The integer pipeline depth now varies depending on the type of instruction, but you’re looking at a range of 14 - 17 stages.

Branch prediction improves tremendously with Silvermont, a staple of any progressive microprocessor architecture. Silvermont takes the gshare branch predictor of Bonnell and significantly increased the size of all associated data structures. Silvermont also added an indirect branch predictor. The combination of the larger predictors and the new indirect predictor should increase branch prediction accuracy.

Couple better branch prediction with a lower mispredict latency and you’re talking about another 5 - 10% increase in IPC over Bonnell.

Introduction & 22nm Sensible Scaling: OoO Atom Remains Dual-Issue
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  • GTRagnarok - Monday, May 6, 2013 - link

    We'll miss you :'( Reply
  • Pheesh - Monday, May 6, 2013 - link

    I don't think the Anandtech site will miss your views and contributions. I appreciated the article and explanations for what's to come. Not everyone cares only about 'specs'. Reply
  • Krysto - Monday, May 6, 2013 - link

    That's what I hate most about Intel's press releases, too. They are typically HIGHLY misleading, in some way or another. Remember when they made people believe the 22nm IVB would be 37% faster AND 40% more efficient? - when it was actually one OR the other, but because of the way they phrased it in the PR...and the way tech sites cloned it in their articles, that's what most people got - that they get BOTH those benefits. In the end it was HALF of each.

    But the worst part about it is the "churnalism" that comes after it. Since most tech sites are either too ignorant or too lazy, they just rewrite what Intel said in the PR - no questions asked.

    Please remember EXACTLY what Intel says Silvermont is capable of - and I PROMISE you when this chip gets reviewed, it won't even seem close, and if you remember everything, you'll be disappointed.
    Reply
  • Khato - Monday, May 6, 2013 - link

    Actually, I don't recall where Intel stating that IVB would be 37% faster AND 40% more efficient. I believe you're confusing technical information regarding the 22nm process capabilities with a product using that process... and incorrectly interpreting that process information to boot. Reply
  • Homeles - Monday, May 6, 2013 - link

    The only thing that I can think of is the chart comparing voltage and gate delay on the first page of this article, which was circulating a lot before the launch of Ivy Bridge. There's nothing misleading about it though, unless you don't know how to read the chart. Reply
  • Homeles - Monday, May 6, 2013 - link

    "That's what I hate most about Intel's press releases, too. They are typically HIGHLY misleading, in some way or another."

    Intel, AMD and Nvidia are all guilty of this, and you know it.
    Reply
  • t.s. - Tuesday, May 7, 2013 - link

    Exactly! Hate it. It looks like all of them have an inferiority complex. They have to boast. Not confident enough with their true offerings. Reply
  • AssBall - Monday, May 6, 2013 - link

    You know I have been coming here for 15 years and thought exactly the same thing. This article is the worst. Terrible PowerPoint graphs and gibberish. No real information. Kind of a sadness. Reply
  • VivekGowri - Monday, May 6, 2013 - link

    The "PowerPoint" graph actually came from Excel, but it came from an article from earlier this year: http://www.anandtech.com/show/6536/arm-vs-x86-the-... (see page 3). And I dare you to find a more thorough or more comprehensively researched and tested article on SoC power consumption literally anywhere else. Reply
  • AssBall - Tuesday, May 7, 2013 - link

    I dared, "literally", but couldn't find much. Sue us for asking for better standards. Reply

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