The mention of Spectre and Meltdown is enough to send chills down any InfoSec spine. A number of these batches of security vulnerabilities deal with speculative execution, and how a processor might leak data while executing code in a speculative manner. This week AMD has pre-empted the security space by detailing a potential security concerns regarding its new Zen 3-based Predictive Store Forwarding feature designed to improve code performance by predicting dependencies between loads and stores. AMD is clear to point out that most users will not need to take any action, as the risk for general consumer use to any breach is low, and no known code is vulnerable.

Predictions Create Predilections for Data

Modern processors use a number of clever techniques to improve performance. A number of those techniques come under the heading of ‘speculation’ – at a high level, when a processor runs code like a simple true/false branch, rather than wait for the result of that true/false check to come in from memory, it will start executing both branches at once. When the true/false result comes back from memory, the branch that had the right answer is kept, and the other is destroyed. Modern processors also predict memory addresses in repetitive loops, or values in a sequence, by learning what code has already been processed. For example, if your loop increments a load address by 1024 bytes every cycle, by the 100th loop, the processor has learned where it expects the next load to come from. It’s all rather clever, and enables a lot of performance.

The downside of these techniques, aside from the extra power consumption needed to execute multiple branches, is the fact that data is in flow from both the correct branch and the incorrect branch at once. That incorrect branch could be accessing data it shouldn’t meant to be and storing it in caches, where it can be read or accessed by different threads. A malicious attacker could cause the incorrect branch to access data it shouldn't be accessing. The concept has lots of layers and is a lot more complicated than I’ve presented here, but in any event, speculation for the sake of performance without consideration to security can lead to fast but leaky data.

For the most part, the whole industry including AMD, Intel, and Arm, have been susceptible to these sort of side-channel attacks. While Meltdown style attacks are more isolated to Intel microarchitectures, Spectre-type attacks are industry wide, and have the potential to leak user memory even in browser-like scenarios.

Predictive Store Forwarding

AMD’s document this week is a security analysis on its new Predictive Store Forwarding (PSF) feature inside Zen 3. PSF identifies execution patterns and commonalities in repeated store/load code, known as store-to-load forwarding. PSF enables the thread to speculate on the next store-to-load result before waiting to see if that result is even needed in the first place. If the result is eventually needed, then we haven’t needed to wait, and the prediction/speculation has done its job and enabled extra performance.

AMD has identified that its PSF feature could be vulnerable in two ways.

First, the pattern of the store-to-load forwarding could change unexpectedly. If the store/load pair is based on a fixed dependency pattern (such as a fixed data stride length using an external multiplier), the PSF feature learns that pattern and continues. If that dependency suddenly changes, or becomes effectively, random, the PSF feature will continue to speculate until it has learned the new dependency pattern. As it continues to speculate during this time, it has the potential to draw unneeded data into the caches which can be probed by external threads, or the access time to that sensitive data will change for external threads, and this can be monitored.

Second, PSF can be vulnerable through memory alignment / aliasing of predictions with dependencies. The PSF is designed to work and track data based on a portion of memory address alignment. As a result, when the store-to-load speculation occurs with an alignment, if a dependency is in the mix of that speculation and the dependency ends up not aligning the predicted values, this might result in incorrect speculation. The data is still valid for a speculation that won’t be used, but therein lies the issue – that data might be sensitive or outside the memory bounds of the thread in question.

Limitations

PSF only occurs within a singular thread – how PSF learns where the next store/load pair should be is individual to each thread. This means that an attack of this nature relies on the underlying code causing the PSF speculation to venture into unintended memory, and cannot be exploited directly by an incoming thread, even on the same core. This might sound as if it becomes somewhat unattackable, however if you have ever used a code simulator in a web-browser, then your code is running in the same thread as the browser.

PSF training is also limited by context – a number of thread-related values (CPL, ASID, PCID, CR3, SMM) define the context and if any one of these is changed, the PSF flushes what it has learned starts a new as an effective new context has been created. Context switching also occurs with system calls, flushing the data as well.

AMD lists that in order to exploit PSF, it requires the store-to-load pairs to be close together in the instruction code. Also the PSF is trained through successive correct branch predictions – a complete mis-prediction can cause a pipeline flush between the store and the load, removing any potential harmful data.

Effect on Consumers, Users, and Enterprise

AMD (and its security partners) has identified that the impact of PSF exploitation is similar to Speculative Store Bypass (Spectre v4), and a security concern arises when code implements security control that can be bypassed. This might occur if a program hosts untrusted code that can influence how other code speculates – AMD cites a web browser might deliver such an attack, similar to other Spectre-type vulnerabilities. 

Despite being similar to other Spectre attacks, AMD’s security analysis states that an attacker would have to effectively train the PSF of a thread with malicious code in the same thread context. This is somewhat difficult to do natively, but could be caused through elevated security accesses. That being said, PSF does not occur across separate address spaces enabled through current hardware mechanisms, such as Secure Encrypted Virtualization. The PSF data is flushed if an invalid data access occurs.

For the enterprise market, AMD is stating that the security risk is mitigated through hardware-based address space isolation. Should an entity not have a way for address space isolation in their deployment, PSF can be disabled though setting either MSR 48h bit 2 or MSR 48h bit 7 to a 1. The only products that would be effected as of today are Ryzen 5000 CPUs and EPYC Milan 7003 CPUs.

AMD is currently not aware of any code in the wild that could be vulnerable to this sort of attack. The security risk is rated as low, and AMD recommends that most end-user customers will not see any security risk by leaving the feature enabled, which will still be the default going forward. 

The full security analysis document, along with a suggested mitigation for enterprise, can be found at this link.

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  • schizoide - Thursday, April 8, 2021 - link

    That's a huge bummer. Since the 5800X is stable it does sound like you got two bad CPUs in a row. Reply
  • Silver5urfer - Thursday, April 8, 2021 - link

    AMD fucked up their TSMC 7N yields. They kept all the top bins to the EPYC Milan and the upcoming Threadripper, where top bins of CCDs go there. And they stamped these crappy CCDs onto the consumer mainstream market thinking yeah it will work as we advertised our performance numbers and results speak for themselves...

    An $800 CPU crashing, to make it worse the RMA also crashes. Not high confidence on AMD with Zen 3 right now.
    Reply
  • Makaveli - Thursday, April 8, 2021 - link

    I would stick to single chiplet cpu's for now 5600X and 5800X seeing less RMA's on those models. And as business it makes sense to push the high quality chips to your enterprise customer who are playing you alot more money than consumers. Reply
  • Makaveli - Thursday, April 8, 2021 - link

    Your issue just sounds like a defective CPU. And you got two of them in a row if you can't run corecycler at default settings. AGESA updates aren't going to fix those issues you have a valid RMA. Reply
  • Spunjji - Thursday, April 8, 2021 - link

    FUD Reply
  • Maverick009 - Friday, April 16, 2021 - link

    Every company has its ups and downs, but AMD has been forthcoming and addressing the issues. When the USB issues became widely reported, AMD was actively communicating in the Reddit forums and asking for users to report it also directly to them on their website so they could get multiple cases built-up and identify the bug. They moved fairly quickly for a company of their size, and board vendors are already implementing the USB fix. There is no major issues with the Curve Optimization ( I am running a 5900X on a Gigabyte Aorus X570 Xtreme v1.1 board). One could talk about Intel, who had several security issues, and now power hungry CPUS that cannot catch up to IP performance AMD has at the moment. Point in case, every company has issues and hiccups now and then. It is how that company chooses to handle it, and I would say they have been handling everything as well as they can and been active with the community. You just need to give it a rest. Reply
  • eva02langley - Thursday, April 8, 2021 - link

    The fact that AMD has put any emphasis on this is making it clear that they will work on fixing this with their upcoming uarchs. Reply
  • Bigos - Thursday, April 8, 2021 - link

    "when a processor runs code like a simple true/false branch, rather than wait for the result of that true/false check to come in from memory, it will start executing both branches at once."

    I don't think any actually-used CPU does that. That is SpMT which was never implemented in practice (I think).

    Instead, a CPU will predict one of the two branches and execute it. It will later revert back in case it is proven it chose the wrong path. It will never execute both paths at the same time.
    Reply
  • hansmuff - Thursday, April 8, 2021 - link

    This is correct!

    If both branches were to execute, it would come at a speed penalty because the compute resources for the 2nd branch have to come from *somewhere*. You wouldn't save performance with prediction hits. Plus, in highly branching code, there would be a good many parellel executions needed.

    Branch prediction misses are expensive for a reason!
    Reply
  • DigitalFreak - Thursday, April 8, 2021 - link

    Waiting to see if Ryan Shart or someone else at Intel has the balls to call out AMD for this, considering all the security issues Intel has had. Reply

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